Since the invention of the integrated circuit, the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit (IC) formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
In an attempt to further increase circuit density, three-dimensional (3D) ICs have been investigated. In a typical formation process of a 3D IC, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, one attempt involved bonding two dies on top of each other. The stacked dies were then bonded to a carrier substrate and wire bonds electrically coupled contact pads on each die to contact pads on the carrier substrate. This attempt, however, requires a carrier substrate larger than the dies for the wire bonding.
More recent attempts have focused on through-silicon vias (TSVs). Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. The backside of the substrate is thinned to expose the TSVs, and solder balls are placed directly on the TSVs to provide an electrical contact. Another die is placed on the solder balls, thereby forming a stacked die package.
The dielectric processes used on the circuit side of the substrate are not applicable to the backside due to the thinned substrate. As a result, the backside of the substrate is left unprotected when the solder balls are placed on the exposed TSVs, limiting the wetting surface for the solder ball without forming electrical shorts between the solder ball and the substrate. Furthermore, the structure limits the mechanical strength with the bonding surface and limits the I/O pin population.
Accordingly, there is a need for a better structure and method of bonding to TSV structures.